1. Field of the Invention
The present invention relates to a voltage regulator for appropriate biasing of electrically programmable non-volatile memory cells. More specifically, the present invention concerns a voltage regulator for programming electrically programmable non-volatile memory cells, wherein the voltage regulator includes an amplifier stage connected and powered between a first and a second reference voltage and having a first input terminal connected to a voltage divider of the first reference voltage, an output terminal connected to the control terminal of a MOS transistor which has its conduction terminal connected to the memory cells through a programming line, and a second input terminal connected to the programming line and connected to the output terminal in a feedback loop.
2. Discussion of the Related Art
As known, electrically programmable non-volatile memory cells are structured in cell matrices, each cell of which includes a floating gate MOS transistor with related drain and source regions. The floating gate is provided over the semiconductor substrate and is separated therefrom by a thin layer of gate oxide. A control gate is capacitatively coupled to the floating gate through a dielectric layer. Metal electrodes are provided for contacting the drain, the source and the control gate to be able to apply predetermined voltage values to the memory cell. By appropriately biasing the cell terminals it is possible to vary the quantity of charge present in the floating gate. The operation by means of which charge is stored in the floating gate is termed `programming` and consists of biasing the drain terminal and the control gate at a predetermined value higher than the potential of the source terminal.
Normally a memory device integrated on a semiconductor substrate includes a very large number of cells of the above mentioned type. The cells are organized in a matrix having rows (termed `word lines`) and columns (termed `bit lines`). The cells belonging to the same word line have a common electric line which drives the respective control gates while the cells belonging to the same bit line have common drain terminals.
The programming of a single memory cell is strongly influenced by the voltage Vpd present on the drain terminal, that is, by the voltage present on the bit line to which it belongs. It is also known that for flash memory cells, a reduced drain voltage value Vpd can result in insufficient or slow cell programming. However, an excessive drain voltage value Vpd can release destructive `snap-back` phenomena or cause partial erasing of the cell, the latter this phenomenon being more commonly known as `soft-erasing`.
The optimal voltage interval for the drain voltage Vpd is rather small, with variations on the order of 200 to 300 millivolts with respect to a typical level, where the typical level varies according to the particular technology used. Thus, the memory device should be equipped with a very refined and accurate voltage regulator to supply the correct voltage to the bit lines during programming. This requirement becomes even more critical when there are a plurality of cells to be programmed simultaneously and in parallel, for example, to reduce the time and cost of the programming operation during testing. In addition, the value of the drain voltage Vpd should be held steady during programming.
It has been found that variations in the drain voltage during programming are essentially linked to the following phenomena: technological variations that are linked to the manufacturing process of the various components of the memory device, an increase in the threshold voltage of the cells during programming and the resulting reduction in the absorbed current, a voltage drop on the power supply line of the programming voltage Vpp, and a voltage drop on the selection transistors present on the bit lines. This last effect can be particularly significant in large-capacity memories in which the selection transistors have a high series resistance. Thus, there is a need to provide a drain voltage regulator accounting for all these phenomena.
The prior art has already proposed different solutions for facing these problems. For example, a typical solution proposed by the prior art provides a regulator whose output voltage is a little higher than that desired on the bit line. The difference in voltage depends instant by instant on the current which actually traverses the selection transistors of the bit line. A regulator of this type is provided by an adaptive biasing technique and through a positive feedback structure. An example of this prior art solution is described in European patent application No. 93830545.5 filed by this same applicant. Although advantageous in some ways, this prior art solution performs its control action on the entire collection of cells and does not allow for a high degree of programming parallelism which could then accelerate the testing phase of the memory device.